The present invention relates to a coding apparatus for generating a convolutional code sequence for use mainly in telecommunications.
In the field of mobile communications, a convolutional code is often used. This is because bit errors, frequently occurring while information is transmitted, require error correction coding after the information has been received. On the other hand, it is indispensable for mobile telecommunications units of today to perform signal processing using a digital signal processor (DSP).
A convolutional code bit is generated by performing addition modulo 2 on an input bit and a number of preceding bits. For example, where the number of preceding bits is K-1, the constraint length is K. And if a number n of bits have been generated with respect to a single input bit, the code rate (which will be herein simply called a xe2x80x9cratexe2x80x9d) is 1/n. FIG. 2 illustrates a configuration for a known convolutional coding apparatus. In the example illustrated in FIG. 2, the convolutional coding apparatus has a constraint length of 4 and a rate of xc2xd.
To generate a convolutional code bit, an exclusive logical sum should be obtained for a bit sequence consisting of the number K of bits, i.e., an input bit and a number K-1 of preceding bits. In getting a program executed by a known DSP using normal instructions, it usually takes several processing steps to code an input bit and obtain one code bit.
Recently, a turbo coding scheme has attracted much attention as a new coding method that can approach the Shannon limit. FIG. 4 is a block diagram illustrating a configuration for a coding apparatus that generates a turbo code sequence. As shown in FIG. 4, the apparatus includes an interleaver 403 and recursive systematic convolutional (RSC) coders 401 and 402. Each of the RSC coders 401 and 402 may have a configuration such as that illustrated in FIG. 5.
Also, Japanese Laid-Open Publication No. 11-46148 discloses a processor that can generate convolutional and turbo code sequences fast enough. FIG. 8 is a block diagram illustrating a processor as disclosed in the publication identified above. FIG. 9 is a circuit diagram illustrating a detailed configuration for the multi-input exclusive OR circuit 780 shown in FIG. 8.
In the processor shown in FIG. 9, a register 760 stores bit select data, from which a convolutional code sequence will be generated. The respective bits of the bit select data are input to a bit selector 770 The multi-input exclusive OR circuit 780 includes three-input, one-output selectors 781. The outputs of the bit selector 770 are supplied as select signals to these three-input, one-output selectors 781.
As also shown in FIG. 9, a shift register 740 stores a number of preceding bits, which are respectively input to the multi-input exclusive OR circuit 780. The output of the multi-input exclusive OR circuit 780 is the convolutional code sequence generated, which will be stored on the shift register 790 shown in FIG. 8.
The known processor shown in FIG. 9, however, needs the bit selector 770. Also, the multi-input exclusive OR circuit 780 is made up of unit construction blocks 783, each including a single exclusive OR gate 782 and a single three-input selector 781. Accordingly, where the constraint length is K, the processor should perform coding by cascading a number K-1 of unit construction blocks 783 together.
A circuit of this type increases its size as the constraint length K increases. In addition, since the unit construction blocks 783 are cascaded, the number of gate stages between its input and output terminals is excessively great. For these reasons, the circuit is not effectively applicable to high-speed processing.
It is therefore an object of the present invention to provide a downsized coding apparatus that can generate a convolutional code sequence much faster.
A coding apparatus according to the present invention includes first shift register, input register and logical operation section. The first shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the first shift register and associated bits stored on the input register and a logical product of each one bit input to the first shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the logical products obtained and then outputs the sum as one bit of a code sequence.
In the inventive apparatus, the logical products of multiple contiguous bits of an input bit sequence and their associated coefficients in the terms on respective orders of a generator polynomial are obtained in parallel. Accordingly, each bit of a code sequence can be obtained in a much shorter time and the convolutional coding process can be carried out far more efficiently. In addition, the values stored on the input register are freely changeable to generate a convolutional code bit in accordance with an arbitrary generator polynomial.
In one embodiment of the present invention, the inventive apparatus preferably further includes a second shift register for storing the input bit sequence thereon. The second shift register preferably performs bit shifting on the input bit sequence and outputs one bit of the input bit sequence after another to the first shift register.
In another embodiment of the present invention, the logical operation section preferably includes: a plurality of AND gates for obtaining the respective logical products; and a plurality of exclusive OR gates for obtaining the exclusive logical sum. The number of gates existing between one of the AND gates and a last-stage one of the exclusive OR gates should be different from the number of gates existing between another one of the AND gates and the last-stage exclusive OR gate by no greater than one.
In such an embodiment, it takes a much shorter time to derive an exclusive logical sum of the logical products obtained, thus speeding up the convolutional coding process.
Where the inventive apparatus includes the second shift register, the apparatus preferably further includes a memory for storing and then outputting the input bit sequence. And the logical operation section preferably gets the code sequence stored on the memory.
In another embodiment, the logical operation section preferably outputs the code sequence to the second shift register. And the second shift register preferably allocates one bit of the code sequence after another to a bit position at which no bit of the input bit sequence is stored anymore as a result of the bit shifting.
An inventive digital signal processor includes the coding apparatus according to any of the foregoing embodiments and an arithmetic and logic unit. In the digital signal processor, the input register is connected to the arithmetic and logic unit.
Another inventive digital signal processor is integrated on the same semiconductor substrate along with the coding apparatus according to any of the foregoing embodiments.
Another inventive coding apparatus includes shift register, first and second input registers and first and second logical operation sections. The shift register performs bit shifting and stores one input bit after another. The first input register stores coefficients of terms on respective orders of a first generator polynomial, while the second input register stores coefficients of terms on respective orders of a second generator polynomial. The first logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the first input register so that the earlier a bit was input to the shift register, the higher-order one of the coefficients in the terms of the first polynomial the input bit is associated with. Next, the first logical operation section derives an exclusive logical sum of the logical products obtained and a currently input bit of an input bit sequence and then outputs the sum to the shift register. The second logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the second input register and a logical product of each one bit input to the shift register and an associated bit stored on the second input register so that the earlier the bit was input to the shift register, the higher-order one of the coefficients in the terms of the second polynomial the input bit is associated with. Next, the second logical operation section derives an exclusive logical sum of the logical products obtained and then outputs the sum as one bit of a code sequence.
An inventive coding method includes the step of performing bit shifting on an input bit sequence and storing one bit of the input bit sequence after another on a shift register. The method further includes the step of obtaining logical products of the respective bits stored on the shift register and associated bits stored on an input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of coefficients in respective terms of a generator polynomial the input bit is associated with. The coefficients of the polynomial are stored on the input register. And the method further includes the step of deriving an exclusive logical sum of the logical products obtained and then outputting the sum as one bit of a code sequence.
Another inventive coding method includes the step of performing bit shifting and storing one input bit after another on a shift register. The method further includes the step of obtaining logical products of the respective bits stored on the shift register and associated bits stored on a first input register so that the earlier a bit was input to the shift register, the higher-order one of coefficients in respective terms of a first generator polynomial the input bit is associated with. The coefficients of the first generator polynomial are stored on the first input register. The method further includes the step of deriving an exclusive logical sum of the logical products obtained and a currently input bit of an input bit sequence and then outputting the sum to the shift register. The method further includes the step of obtaining logical products of the respective bits stored on the shift register and associated bits stored on a second input register and a logical product of each one bit input to the shift register and an associated bit stored on the second input register so that the earlier the bit was input to the shift register, the higher-order one of coefficients in respective terms of a second generator polynomial the input bit is associated with. The coefficients of the second generator polynomial are stored on the second input register. And the method further includes the step of deriving an exclusive logical sum of the logical products obtained and then outputting the sum as one bit of a code sequence.
Still another inventive digital signal processor realizes a coding method according to any of the two aspects of the present invention described above by executing a single instruction.